The present invention relates to an array substrate, and more particularly, to an array substrate being capable of preventing a disconnection in a jumper portion and a method of fabricating the array substrate.
As society has entered the information age, a field of display devices that visually represent all sorts of electrical signals as images has developed rapidly. Particularly, liquid crystal display (LCD) devices or organic light emitting diode (OELD) display devices as a flat panel display device having characteristics of light weight, thinness and low power consumption have been developed for use as a substitute for a cathode-ray tube type display devices.
Since LCD devices include a thin film transistor (TFT) as a switching element, referred to as an active matrix LCD (AM-LCD) device, they have excellent characteristics of high resolution for displaying moving images and have been widely used.
On the other hand, since OELD devices have excellent characteristics of high brightness, low power consumption and high contrast ratios, OELD display devices have also been widely used. Moreover, OELD display devices have advantages of a high response rate, a low production cost and so on.
Both LCD devices and the OELD display devices require an array substrate including a thin film transistor (TFT) as a switching element for controlling on and off states of each pixel region. In addition, OELD devices requires another TFT as a driving element for driving an organic electroluminescent diode in each pixel region.
Recently, to meet the requirements of light-weight, thinness and reduced production costs, a gate driving circuit is formed directly on a non-display region of a substrate. It may be referred to as a gate-in-panel (GIP) structure array substrate.
The GIP structure array substrate includes a display region for displaying images, a pad part at an upper portion of the display region, a gate circuit part at a side portion of the display region and a signal input part at a side of the circuit part.
The gate circuit part is connected to each gate line and includes a driving block. In the driving block, a plurality of driving TFTs, which are connected to each other, are formed.
FIG. 1 is a schematic plane view of a non-display region of the related art GIP structure array substrate, and FIG. 2 is a cross-sectional view taken along II-II line of FIG. 1.
As shown in FIGS. 1 and 2, on a substrate, a gate line (not shown) is formed in a display region (not shown), and a first auxiliary line 7 and a first auxiliary pattern 8, which is connected to the first auxiliary line 7, are formed in a non-display region NA. A layer, where the gate line, the first auxiliary line 7 and the first auxiliary pattern 8 are disposed, is referred to as a gate layer. A gate insulating layer 10 is formed on the gate layer, i.e., the gate line, the first auxiliary line 7 and the first auxiliary pattern 8. On the gate insulating layer 10, a source electrode (not shown) and a drain electrode (not shown) are formed in the display region, and a second auxiliary line 37 and a second auxiliary pattern 38, which is connected to the second auxiliary line 37, are formed in a non-display region NA. A layer, where the source electrode, the drain electrode, the second auxiliary line 37 and the second auxiliary pattern 38 are disposed, is referred to as a source-drain layer. A passivation layer 50 is formed to cover the source electrode, the drain electrode, the second auxiliary line 37 and the second auxiliary pattern 38.
First and second contact holes ch1 and ch2, which respectively expose the first and second auxiliary patterns 8 and 38, are formed through the passivation layer 50.
A connection pattern 63 is formed on the passivation layer 50. One end of the connection pattern 63 contacts the first auxiliary pattern 8 through the first contact hole ch1, and the other end of the connection pattern 63 contacts the second auxiliary pattern 38 through the second contact hole ch2. As a result, the first and second auxiliary patterns 8 and 38 are electrically connected to each other. Namely, there is a jumper portion for providing an electrical connection between the gate layer, i.e., the first auxiliary pattern 8, and the source-drain layer, i.e., the second auxiliary pattern 38. The connection pattern 63 is formed at the same layer as a pixel electrode in each pixel region of the display region.
In order to reduce the production costs and simplify the fabrication process, a semiconductor layer (not shown) and the source and drain electrodes are formed by a single mask process. As a result, under the second auxiliary pattern 38, which is formed at the source-drain layer, a dummy semiconductor pattern 21, which includes first and second dummy patterns 21a and 21b, is formed. The dummy semiconductor pattern 21 is formed at the same layer and of the same material as the semiconductor layer.
Since the first and second dummy patterns 21a and 21b and the second auxiliary pattern 38 are formed by a single mask process, ends of the first dummy pattern 21a protrude beyond the second auxiliary pattern 38. It may be referred to as an active tail.
In the mask process, a center portion of an ohmic contact layer, which is formed of impurity-doped amorphous silicon, of the semiconductor layer, should be etched by a dry-etching process, however the gate insulating layer 10 is also undesirably etched. As a result, the gate insulating layer 10 has an undercut structure at peripheries of the first dummy pattern 21a. 
In addition, the passivation layer 50, which is formed to cover the gate insulating layer 10 and the second auxiliary pattern 38, has an undercut structure due to the undercut structure of the gate insulating layer 10. Accordingly, the connection pattern 63 (e.g., the jumper portion), which is formed on the passivation layer 50 to connect the first and second auxiliary patterns 8 and 38, has a problem of disconnecting.